AX2061 Datasheet, PDF (1/18 Pages) ON Semiconductor – LCD Driver for Low Multiplex Rates

AX2061
LCD Driver for Low
Multiplex Rates
OVERVIEW
The AX2061 is an LCD driver for low multiplex rates. Figure 1
shows the block diagram of the AX2061. The chip is controlled by a
microcontroller using the SPI interface. The microcontroller writes
pixel (segment) data into the pixel data memory. Display updates may
be delayed using the pixel data latches. The pixel data latches drive the
segment drivers, while the row counter drives the row drivers.
Features
• Single−chip LCD Controller/Driver 5 Row, 76 Segment Outputs
• Wide Power Supply Range: from 2.2 V to 3.6 V
• 4−bit Contrast Register
• Selectable Row Drive Configuration: Static or 2/3/4/5 Row
Multiplexing
• Internal Generation of LCD Bias Voltages with Charge Pump
from a Single 2.2 to 3.6 V Power Supply
• 76 × 5−bit RAM for Display Data Storage
• Auto−incremented Display Data Loading
• Low Power Consumption
• Internal 32 kHz Oscillator
• SPI−Bus Interface
BLOCK DIAGRAM
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ORDERING INFORMATION
Device
Package
Shipping
AX2061−1−WD1 Wafer/Die Contact Sales
See additional information on page 16 of this data sheet.
VDD
ICLK
RREF
SYSCLK (32kHz)
optional
LATCH
VSS
SEL
CLK
MOSI
MISO
optional
CAP
Voltage Regulator / Pump
Oscillator
32 kHz
Frequency
Divider
Pixel
Address
Counter
SPI
Row Drivers
Frame
Counter
ROW#
ROW#
SEG#
Segment Drivers
Pixel Latches
Pixel Data Registers
Figure 1. Functional Block Diagram of the AX2061
© Semiconductor Components Industries, LLC, 2016
1
March, 2016 − Rev. 3
Publication Order Number:
AX2061/D