ASM5P2308A Datasheet, PDF (1/11 Pages) Alliance Semiconductor Corporation – 3.3V Zero-Delay Buffer

ASM5P2308A
3.3 V Zero-Delay Buffer
Description
ASM5P2308A is a versatile, 3.3 V zero−delay buffer designed to
distribute high−speed clocks. It is available in a 16−pin package. The
part has an on−chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input−to−output
propagation delay is guaranteed to be less than ±250 pS, and the
output−to−output skew is guaranteed to be less than 200 pS.
The ASM5P2308A has two banks of four outputs each, which can
be controlled by the select inputs as shown in the Select Input
Decoding Table. If all the output clocks are not required, Bank B can
be three−stated. The select input also allows the input clock to be
directly applied to the outputs for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input clock
and distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 pS.
ASM5P2308A is available in five different configurations. Refer to
ASM5P2308A Configurations Table. The ASM5P2308A−1 is the base
part, where the output frequencies equal the reference clock input. The
ASM5P2308A−1H is the high−drive version of the −1 and the rise and
fall times on this device are faster.
ASM5P2308A−2 allows the user to obtain 2x and 1x frequencies on
each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. ASM5P2308A−3
allows the user to obtain 4x and 2x frequencies on the outputs.
ASM5P2308A−4 enables the user to obtain 2x clocks on all outputs.
The ASM5P2308A−5H is a high−drive version with REF/2 output
on both banks.
ASM5P2308A is an extremely versatile part, and can be used in a
variety of applications.
Features
• Zero Input−output Propagation Delay, Adjustable by Capacitive Load
on FBK Input
• Multiple Configurations –
Refer to ASM5P2308A Configurations Table
• Input Frequency Range: 10 MHz to 133 MHz
• Multiple Low−skew Outputs
♦ Output−output Skew less than 200 pS
♦ Device−device Skew less than 700 pS
♦ Two Banks of Four Outputs Each,
Three−state by Two Select Inputs
• Less than 200 pS Cycle−to−Cycle Jitter (−1, −1H, −2, −3, −4, −5H)
• 16−pin SOIC and TSSOP Packages
• 3.3 V Operation
• Commercial and Industrial Temperature Range
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
SOIC−16
S SUFFIX
CASE 751BG
TSSOP−16
T SUFFIX
CASE 948AN
PIN CONFIGURATION
1
REF
FBK
CLKA1
CLKA4
CLKA2
CLKA3
V_DD
GND
V_DD
GND
CLKB1
CLKB4
CLKB2
CLKB3
S2
S1
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
August, 2011 − Rev. 3
Publication Order Number:
ASM5P2308A/D