AP0100CS Datasheet, PDF (1/73 Pages) ON Semiconductor – High-Dynamic Range (HDR) Image Signal Processor (ISP)

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AP0100CS HDR: Image Signal Processor (ISP)
Features
AP0100CS High-Dynamic Range (HDR) Image
Signal Processor (ISP)
AP0100CS Datasheet, Rev. 6
For the latest product datasheet, please visit www.onsemi.com
Features
• Up to 1.2Mp (1280x960) ON Semiconductor sensor
support
• 45 fps at 1.2Mp, 60 fps at 720p
• Optimized for operation with HDR sensors.
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Programmable Spatial Transform Engine (STE).
• Pre-rendered Graphical Overlay
• Two-wire serial programming interface (CCIS)
• Interface to low-cost Flash or EEPROM through SPI
bus (to configure and load patches, etc.)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
Applications
• IP cam and CCTV - HD
• Enables CCTV -HD w/ MP sensor
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interfaces
Parallel and HiSPi
Primary camera input
RAW12 Linear/RAW12, RAW14 (HiSPi
format only) Companded
Output interface
Analog composite, up to 16-bit
parallel digital output
Output format
YUV422 8-bit,10-bit, and 10-, 12-bit
tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
NTSC output
720H x 487V
PAL output
720H x 576V
Input clock range
6-30 MHz
VDDIO_S
1.8 or 2.8 V nominal
VDDIO_H
2.5 or 3.3 V nominal
VDD_REG
1.8 V nominal
VDD
1.2 V nominal
Supply voltage
VDD_PLL
1.2 V nominal
VDD_DAC
1.2V nominal
VDDIO_OTPM 2.5 or 3.3 V nominal
VDDA_DAC
3.3 V nominal
VDD_PHY
2.8 V nominal
Operating temp.
–30°C to +70°C
Power consumption 185 mW
Notes: 1.
AP0100CS/D Rev. 6, 1/16 EN
1
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