AND8009 Datasheet, PDF (1/67 Pages) ON Semiconductor – ECLinPS Plus SPICE Modeling Kit

AND8009/D
ECLinPS Plus™
SPICE Modeling Kit
Prepared by:
Senad Lomigora, Paul Shockman
ON Semiconductor Broadband Applications Engineering
http://onsemi.com
APPLICATION NOTE
Objective
The objective of this kit is to provide customers with
enough circuit schematic and SPICE parameter information
to allow them to perform system level interconnect
modeling for the current devices of the ECLinPS Plus logic
line, ON Semiconductor’s high performance ECL family.
The kit is not intended to provide information necessary
to perform circuit level modeling on ECLinPS Plus
devices. With packaged gate delays of 160 ps and output
edge rates as low as 80 ps, this family defines the
state−of−the−artin ECL logic. The ECLinPS Plus line is one
of ON Semiconductor’s high performance ECL/PECL
family of products.
Schematic Information
The kit contains representative input and output
schematics, netlists, and waveform used for the ECLinPS
Plus devices. This application note will be modified as new
devices are added. The subcircuit models such as the input
or output buffer, package, input ESD and output ESD may
be interconnected as subcircuits to simulate specific device
characteristics as shown in Figure 1 below. The block
diagram in Figure 2 illustrates a typical situation which can
be modeled using the information in this kit.
Board Pin
Connection
Subcircuit Interconnects for Input Pins
Package
Model
Input ESD
Model
Input Buffer
Model
Output Buffer
Model
Subcircuit Interconnects for Output Pins
Output ESD
Model
Package
Model
Board Pin
Connection
Figure 1. Input and Output Pins Interconnects
Typical Output
50 W
6” Line
50 W
3” Line
50 W
10” Line
Typical Input
Typical Input
Typical Input
50 W
V_TT
Figure 2. Typical Application for I/O SPICE Modeling Kit
© Semiconductor Components Industries, LLC, 2004
1
February, 2004 − Rev. 10
Publication Order Number:
AND8009/D