AN1568 Datasheet, PDF (1/10 Pages) ON Semiconductor – Interfacing Between LVDS and ECL

AN1568/D
Interfacing Between LVDS
and ECL
Prepared by: Paul Lee
Logic Applications Engineer
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Introduction
Recent growth in high−speed data transmission between
high−speed ICs demand more bandwidth than ever before
while still maintaining high performance, low power
consumption and good noise immunity. Emitter Coupled
Logic (ECL) recognized the challenge and provided high
performance and good noise immune devices. ECL
migrated toward low voltages to reduce the power
consumption and to keep up with current technology trends
by offering 3.3 V and 2.5 V Low Voltage ECL (LVECL)
devices.
LVDS (Low Voltage Differential Signaling) technology
also addresses the needs of current high performance
applications. LVDS as specified in ANSI/TIA/EIA−644 by
Data Transmission Interface committee TR30.2 and IEEE
1596.3 SCI−LVDS by IEEE Scalable Coherent Interface
standard (SCI) is a high speed, low power interface that is a
solution in many application areas. LVDS provides an
output swing of 250 mV to 400 mV with a DC offset of 1.2 V.
External resistor components are required for
board−to−board data transfer or clock distribution.
LVECL and LVDS are both differential voltage signals,
but with different output amplitude and offset. The purpose
of this documentation is to show the interfacing between
LVECL and LVDS. In addition, it gives interface
recommendations to and from 5.0 V supplied PECL devices
and negative supplied ECL or NECL
ECL levels
Today’s applications typically use ECL devices in the
PECL mode. PECL (Positive ECL) is nothing more than
supplying any ECL device with a positive power supply
(V_CC = +5.0 V, V_EE = 0 V). In addition, ECL uses differential
data transmission technology, which results in better noise
immunity. Since the common mode noise is coupled onto the
differential interconnect, it will be seen as a common mode
modulation and will be rejected.
With the trend towards low voltage systems, a new
generation of ECL circuitry has been developed. The Low
Voltage NECL (LVNECL) devices work using negative
–3.3 V or –2.5 V power supply, or more popular positive
power supplies, V_CC = +3.3 V or +2.5 V and V_EE = GND as
LVPECL. LVECL maintains 750 mV output swing with a
0.9 V offset from V_CC, which makes them ideal as peripheral
components.
The temperature compensated (100EL, 100LVEL,
100EP, 100LVEP) output DC levels for the different supply
levels are shown in Table 1. ECL outputs are designed as an
open emitter, requiring a DC path to a more negative supply
than V_OL. (see AND8020 for ECL Termination
information).
ECL standard DC input levels are also relative to V_CC.
Many devices are available with Voltage Input HIGH
Common Mode Range (V_IHCMR). These differential inputs
allow processing signals with small V_INPPMIN (down to
200 mV, 150 mV or even 50 mV signal levels) within an
appropriate offset range. The V_IHCMR ranges of ECL
devices are listed in each respective data sheets.
© Semiconductor Components Industries, LLC, 2003
1
October, 2003 − Rev. 8
Publication Order Number:
AN1568/D