AN1504 Datasheet, PDF (1/8 Pages) ON Semiconductor – Metastability and the ECLinPS Family

AN1504/D
Metastability and the
ECLinPS Family
Prepared by: Applications Engineering
http://onsemi.com
APPLICATION NOTE
This application note examines the concept of
metastability and provides a theoretical discussion of how it
occurs, including examples of the metastable condition. An
equation characterizing metastability and a test circuit
derived from that equation are presented. Metastability
results are then applied to the ECLinPS family.
Introduction
Metastability is a central issue anytime a designer wishes
to synchronize two or more asynchronous signals. A popular
method for accomplishing this task is to employ a D
flip−flop as the synchronizing element (Figure 1).
As shown in Figure 1, synchronization can be
accomplished using a single D flip−flop; more typically,
several D flip−flops are cascaded to provide synchronization
while reducing the probability of a metastable or
“anomalous” state occurring at the input of System 2.
Unfortunately the information at the data and clock inputs of
flip−flops used as synchronizing elements is asynchronous by
nature, thus the manufacturer specifications for set−up and
hold times may not be observed. A series of timing diagrams
is shown in Figure 2 demonstrating three possible timing
relationships between the data and clock signals; to the right
of each data trace is the corresponding output waveform. In
the first case the data adheres to the specified set−up and hold
times, hence the output attains the proper state. In case 2 the
set−up time is violated such that the output of the D flip−flop
does not change state. Case 3 represents a violation of the
set−up and hold times whereby the D flip−flop enters a
metastable state. The resolving time for a flip−flop in this
metastable state is indeterminate. Further, the final settling
state of the flip−flop having been in this metastable condition
cannot be guaranteed.
Metastability Theory
A bistable device such as a flip−flop has two stable output
states: the “1” or high state and the “0” or low state. When
the manufacturers specified set−up and hold times are
observed the flip−flop will achieve the proper output state
(Figure 3). However if the set−up and hold times are
violated the device may enter a metastable state, thereby
increasing the propagation delay, as indicated by the output
response shown in Figure 4.
To better understand flip−flop metastability, the operation
of a typical ECLinPS D flip−flop is reviewed. The schematic
of a D flip−flop is shown in Figure 5.
SYSTEM 1
CLOCK
SYSTEM 2
CLOCK
SYSTEM 1
CLOCK
SYSTEM 2
CLOCK
SYSTEM 1
SYSTEM 1
OUTPUT
SYSTEM 1
SYSTEM 1
OUTPUT
DATA
Q
D FLIP−FLOP
CLOCK
DATA
Q
D FLIP−FLOP
CLOCK
DATA
Q
D FLIP−FLOP
CLOCK
SYSTEM 2 INPUT
SYSTEM 2
SYSTEM 2 INPUT
SYSTEM 2
T_D DELAY
Figure 1. Clock Synchronization Schemes
 Semiconductor Components Industries, LLC, 2004
1
November, 2004 − Rev. 2
Publication Order Number:
AN1504/D