74ALVCH16245 Datasheet, PDF (1/12 Pages) ON Semiconductor – Low-Voltage 16-Bit Transceiver with Bus Hold 1.8/2.5/3.3 V(3-State, Non-Inverting)

74ALVCH16245
Low-Voltage 16-Bit
Transceiver with Bus Hold
1.8/2.5/3.3 V
(3–State, Non–Inverting)
The 74ALVCH16245 is an advanced performance, non–inverting
16–bit transceiver. It is designed for very high–speed, very low–power
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16245 is designed with byte control. It can be
operated as two separate octals, or with the controls tied together, as a
16–bit wide function. The Transmit/Receive (T/Rn) inputs determine
the direction of data flow through the bi–directional transceiver.
Transmit (active–HIGH) enables data from A ports to B ports; Receive
(active–LOW) enables data from B to A ports. The Output Enable
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition. The data inputs include active bushold
circuitry, eliminating the need for external pull–up resistors to hold
unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: V_CC = 1.65 – 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• I_OFF Specification Guarantees High Impedance When V_CC = 0 V^†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16245
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP–48
DT SUFFIX
CASE 1201
74ALVCH16245DT
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
74ALVCH16245DTR TSSOP 2500/Tape & Reel
†To ensure the outputs activate in the 3–state condition, the output enable pins
should be connected to V_CC through a pull–up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2002
1
September, 2002 – Rev. 1
Publication Order Number:
74ALVCH16245/D