74ALVCH16240 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold

74ALVCH16240
Low−Voltage 16−Bit Buffer
with Bus Hold 1.8/2.5/3.3 V
(3−State, Inverting)
The 74ALVCH16240 is an advanced performance, inverting 16−bit
buffer. It is designed for very high−speed, very low−power operation
in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16240 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16−bit operation. The 3−state outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bus−hold
circuitry, eliminating the need for external pull−up resistors to hold
unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: V_CC = 1.65 to 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High−Speed Operation: 3.0 ns Max for 3.0 to 3.6 V
3.7 ns Max for 2.3 to 2.7 V
6.0 ns Max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bus−Hold to Hold Unused or Floating Inputs at a
Valid Logic State
• I_OFF Specification Guarantees High Impedance When V_CC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16240
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
74ALVCH16240DT
AWLYYWW
1
A
= Assembly
Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
ORDERING INFORMATION
Device
Package
74ALVCH16240DTR
TSSOP
Shipping
2500 / Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to V_CC through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 3
Publication Order Number:
74ALVCH16240/D