2N5684G Datasheet, PDF (1/5 Pages) ON Semiconductor – High-Current Complementary Silicon Power Transistors

2N5684 (PNP), 2N5686 (NPN)
High-Current
Complementary Silicon
Power Transistors
These packages are designed for use in high-power amplifier and
switching circuit applications.
Features
•ăHigh Current Capability - I_C Continuous = 50 Amperes
•ăDC Current Gain - h_FE = 15ā-ā60 @ I_C = 25 Adc
•ăLow Collector-Emitter Saturation Voltage -
ąV_CE(sat) = 1.0 Vdc (Max) @ I_C = 25 Adc
•ăPb-Free Packages are Available*
MAXIMUM RATINGS (Note 1)
Rating
Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage
Collector Current - Continuous
Base Current
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
Symbol
V_CEO
V_CB
V_EB
I_C
I_B
P_D
Value
80
80
5.0
50
15
300
1.715
Unit
Vdc
Vdc
Vdc
Adc
Adc
mW
mW/°C
Operating and Storage Temperature
Range
T_J, T_stg -ā65 to +ā200 °C
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Thermal Resistance, Junction-to-Case
qJC
0.584
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Indicates JEDEC Registered Data.
300
250
200
150
http://onsemi.com
50 AMPERE
COMPLEMENTARY SILICON
POWER TRANSISTORS
60-80 VOLTS, 300 WATTS
MARKING
DIAGRAM
TO-204 (TO-3)
CASE 197A
STYLE 1
2N568xG
AYYWW
MEX
2N568x
G
A
YY
WW
MEX
= Device Code
x = 4 or 6
= Pb-Free Package
= Location Code
= Year
= Work Week
= Country of Orgin
ORDERING INFORMATION
Device
2N5684G
2N5686
Package
TO-3
(Pb-Free)
TO-3
Shipping
100 Units/Tray
100 Units/Tray
2N5686G
TO-3
(Pb-Free)
100 Units/Tray
100
50
0
0 20 40 60 80 100 120 140 160 180 200
TEMPERATURE (°C)
Figure 1. Power Derating
*For additional information on our Pb-Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Safe Area Curves are indicated by Figure 5. All limits are applicable and must be observed.
©Ă Semiconductor Components Industries, LLC, 2007
1
October, 2007 - Rev. 12
Publication Order Number:
2N5684/D