MSM51V17805B Datasheet, PDF (8/8 Pages) OKI electronic componets – 2,097,152-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

MSM51V17805B/BSL
¡ Semiconductor
Notes:
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t_T = 2 ns.
3. V_IH (Min.) and V_IL (Max.) are reference levels for measuring input timing signals.
Transition times (t_T) are measured between V_IH and V_IL.
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are V_OH = 2.0 V and V_OL = 0.8 V.
5. Operation within the t_RCD (Max.) limit ensures that t_RAC (Max.) can be met.
t_RCD (Max.) is specified as a reference point only. If t_RCD is greater than the specified
t_RCD (Max.) limit, then the access time is controlled by t_CAC.
6. Operation within the t_RAD (Max.) limit ensures that t_RAC (Max.) can be met.
t_RAD (Max.) is specified as a reference point only. If t_RAD is greater than the specified
t_RAD (Max.) limit, then the access time is controlled by t_AA.
7. t_CEZ (Max.), t_REZ (Max.), t_WEZ (Max.) and t_OEZ (Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. t_CEZ and t_REZ must be satisfied for open circuit condition.
9. t_RCH or t_RRH must be satisfied for a read cycle.
10. t_WCS, t_CWD, t_RWD, t_AWD and t_CPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If t_WCS ≥ t_WCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t_CWD ≥ t_CWD (Min.) , t_RWD ≥ t_RWD (Min.),
t_AWD ≥ t_AWD (Min.) and t_CPWD ≥ t_CPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
14. Only SL version.
See ADDENDUM O for AC Timing Waveforms
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