MSM5299A Datasheet, PDF (7/11 Pages) OKI electronic componets – 80-DOT LCD SEGMENT DRIVER

¡ Semiconductor
MSM5299A
FUNCTIONAL DESCRIPTION
Pin Functional Description
• ER, EL
Pin
Input/Output
SHL
Description
ER
Input
Input pin to ENABLE F/F of MSM5299A.
EL
Output
L
Output pin of ENABLE F/F. EL is connected to next MSM5299A's
ER when MSM5299As are connected in series (cascade
connection).
EL
Input
Input pin to ENABLE F/F of MSM5299A.
ER
Output
H
Output pin of ENABLE F/F. ER is connected to next MSM5299A's
EL when MSM5299As are connected in series (cascade
connection).
When single MSM5299A is used, ER (EL) should be set at "L" level.
When a cascade connection is required, set the ER (EL) pin of the first MSM5299A at "L" level
and connect the EL (ER) pin of the first MSM5299A to the ER (EL) pin of the second MSM5299A,
then connect the EL (ER) pin of the second MSM5299A to the ER (EL) pin of the third MSM5299A.
• CP
Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to 4 ¥ 20-bit shift
register at the falling edge of the clock pulse. The clock pulse is activated when the ENABLE
F/F is set and is deactivated when the ENABLE F/F is not set.
• SHL
Input pin to switch the input or output of pins ER and EL, and the shift direction of the 4-bit
parallel bidirectional shift register.
The shift direction of the 4-bit parallel data, the correspondence of the data D₀ to D₃ to the
driver outputs O₁ to O₈₀, and the input and output state of pins ER and EL are shown in the
table below.
SHL
L
H
ER
Input
EL
Output
Output
Input
Shift direction
D₀
O₁
O₅
O₇₇
D₁
O₂
O₆
O₇₈
D₂
O₃
O₇
O₇₉
D₃
O₄
O₈
O₈₀
D₀
O₈₀
O₇₆
O₄
D₁
O₇₉
O₇₅
O₃
D₂
O₇₈
O₇₄
O₂
D₃
O₇₇
O₇₃
O₁
end data
start data
7/11