MS8104166 Datasheet, PDF (6/19 Pages) OKI electronic componets – Dual FIFO (262,214 Words × 8 Bits) × 2

1Semiconductor
PEDS8104166-01
MS8104166
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE1, 2 is high during a
read operation. The SRCK input increments the internal read address pointer when RE1, 2 is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval t_AC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS8104166.
Data Input: (DIN20 to 27)
These pins are used for serial data inputs.
Write Reset: RSTW2
The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW2
setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely
controlled by the SWCK rising edge after the high level of RSTW2, the states of WE2 and IE2 are ignored in the
write reset cycle. Before RSTW2 may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Write Enable: WE2
WE is used for data write enable/disable control. WE2 high level enables the input, and WE2 low level disables the
input and holds the internal write address pointer. There are no WE2 disable time (low) and WE2 enable time
(high) restrictions, because the MS8104166 is in fully static operation as long as the power is on. Note that WE2
setup and hold times are referenced to the rising edge of SWCK.
Input Enable: IE2
IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The internal write address
pointer is always incremented by cycling SWCK regardless of the IE2 level. Note that IE2 setup and hold times are
referenced to the rising edge of SWCK.
Data Out: (DOUT20 to 27)
These pins are used for serial data outputs.
Read Reset: RSTR2
The first positive transition of SRCK after RSTR2 becomes high resets the read address pointers to zero. RSTR2
setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled
by the SRCK rising edge after the high level of RSTR2, the states of RE2 and OE2 are ignored in the read reset
cycle. Before RSTR2 may be brought high again for a further reset operation, it must be low for at least *two
SRCK cycles.
Output Enable: OE2
OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal read address pointer is
always incremented by cycling SRCK regardless of the OE2 level. Note that OE2 setup and hold times are
referenced to the rising edge of SRCK.
Mode Setting: MODE1
The Cascade/Non cascade select pin. Setting the MODE1 pin to the V_CC level configures this memory device as
cascade type and setting the pin to the V_SS level configures this memory device as non cascade. During memory
operation, the pin must be permanently connected to V_CC or V_SS. If a MODE1 level is changed during memory
operation, memory data is not guaranteed.
Note: Cascade/Non cascade
When MODE1 is set to the V_SS level, memory accessing starts in the cycle in which the control signals are input
(Non cascade type). When MODE1 is set to the V_CC level, memory accessing starts in the cycle subsequent to the
cycle in which the control signals are input (Cascade type). This type is used for consecutive memory accessing.
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