ML60852 Datasheet, PDF (57/81 Pages) OKI electronic componets – USB Device Controller

1Semiconductor
PEDL60852-01
ML60852
EP3 Payload Register (EP3PLD)
Address
Type
Access type
0 x 53
6-Bit data
Read/Write
D7 D6 D5 D4 D3 D2 D1 D0
After a hardware reset 0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
0
0
Maximum packet size
(R/W)
Maximum packet size: Make the local MCU write in this register the value of the descriptor wMaxPacketSize of
the end point selected by the Set_Configuration request from the host. The size of all
packets other than a short packet is specified here in units of a byte. Set 20h (32 bytes) or
less because the FIFO size is 32 bytes.
When EP3 has been assigned for reception, if a data packet with a number of bytes
exceeding the maximum packet size specified in this register is received, the receive
packet ready status bit is not asserted, but the stall bit is set in EOP and the stall handshake
is returned to the host.
There is no need to use this register when EP3 has been assigned for transmission.
EP4, 5 Payload LSB Registers (EP4, 5PLDLSB)
Address
Type
Access type
0 x 54, 55
10-Bit or 9-bit data
Read/Write
D7 D6 D5 D4 D3 D2 D1 D0
After a hardware reset 0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
Maximum packet size LSB (R/W)
Maximum packet size LSB: Make the local MCU write in this register the value of the descriptor wMaxPacketSize
of the end point selected by the Set_Configuration request from the host. The lower 8
bits should be stored in this register and the higher-order bytes should be written in the
EP4,5 payload registers MSB. The maximum packet size is specified in units of a
byte.
When the EP has been assigned for reception, if a data packet with a number of bytes
exceeding the maximum packet size specified in these registers is received, the receive
packet ready status bit is not asserted, but the stall bit is set in EOP and the stall
handshake is returned to the host.
On the other hand, when the EP has been assigned for transmission, the transmit
packet ready bit is set automatically when writing by the DMA controller of data with
the maximum packet size specified in this register is completed.
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