ML60851C Datasheet, PDF (55/67 Pages) OKI electronic componets – USB Device Controller

¡ Semiconductor
PEDL60851C-02
ML60851C
DMA Transfer Timing (4)
ML60851C to Memory (Demand Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
CS Hold Time
Read Data Delay Time
Data Hold Time
Recovery Time
Symbol
t₁
t₂
t₃
t₄
t₅
Condition
Load 20 pF
Load 20 pF
Load 20 pF
8-bit DMA
16-bit DMA
Min.
—
0
—
0
63
105
Max.
20
—
25
25
—
—
Unit Note
ns
ns
ns
1
ns
ns
2
ns
3
Notes: 1. When in Dual Address mode, the DACK is ignored.
t₃ is defined depending on CS or RD which becomes active last.
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
CS
RD
DOUT
t₅
t₄
t₃
t1
t₂
Last Packet Read
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