MSM60808 Datasheet, PDF (49/92 Pages) OKI electronic componets – PCI to PCMCIA R2.1/CardBus Controller (PPCC)

¡ Semiconductor
MSM60808
5.1.37 Buffer Control Register (BFFCTL)
Register offset
Default value
Access
Size
: 93h
: 00h
: Read/write
: 8-bit
This register is used to control the depth of FIFO. However, data transfers of configulation
commands and I/O commands are not effected by this register setting.
76543210
PCI Bus Write FIFO Control
PCI Bus Read FIFO Control
CardBus Write FIFO Control
CardBus Read FIFO Control
Reserved (0)
Bit
Bit [7:4]
Bit 3
Bit 2
Bit 1
Bit 0
Description
These reserved bits are fixed to 0h.
The CardBus Read FIFO Control bit controls the depth of the FIFO when reading from the master
CardBus card. When this bit is 0, data can be transferred up to the maximum depth of the FIFO.
When 1, 4-byte transfers (4-byte signal transfer only) are allowed. This bit will be 0 after reset.
The CardBus Write FIFO Control bit controls the depth of the FIFO when writing from the master
CardBus card. When this bit is 0, data can be transferred up to the maximum depth of the FIFO.
When 1, 4-byte transfers (4-byte signal transfer only) are allowed. This bit will be 0 after reset.
The PCI Bus Read FIFO Control bit controls the depth of the FIFO when the PCI bus master reads
data from a card. When this bit is 0, data can be transferred up to the maximum depth of the
FIFO. When 1, 4-byte transfers (4-byte signal transfer only) are allowed. This bit will be 0 after reset.
The PCI Bus Write FIFO Control bit controls the depth of the FIFO when writing from the PCI bus.
When this bit is 0, data can be transferred up to the maximum depth of the FIFO. When 1, 4-byte
transfers (4-byte signal transfer only) are allowed. This bit will be 0 after reset.
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