MSM66591 Datasheet, PDF (375/466 Pages) OKI electronic componets – CMOS 16-bit microcontroller

MSM66591/ML66592 User's Manual
Chapter 16 A/D Converter Functions
[10] A/D Hard Select Enable Register (ADHENCON)
ADHENCON is an 8-bit register that controls enable/disable of the hard select mode for
each channel (ch0, ch1, ch2, ch3, ch12, ch13, ch14, ch15).
Figure 16-16 shows the configuration of ADHENCON.
At reset (when the RES signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), ADHENCON becomes 00H.
<Description of Each Bit>
• ADHENC0 (bit 0)
This bit enables or disables hard select A/D conversion on channel 0.
If this bit is "1", the hard select of channel 0 is enabled, and if "0", disabled.
• ADHENC1 (bit 1)
This bit enables or disables hard select A/D conversion on channel 1.
If this bit is "1", the hard select of channel 1 is enabled, and if "0", disabled.
• ADHENC2 (bit 2)
This bit enables or disables hard select A/D conversion on channel 2.
If this bit is "1", the hard select of channel 2 is enabled, and if "0", disabled.
• ADHENC3 (bit 3)
This bit enables or disables hard select A/D conversion on channel 3.
If this bit is "1", the hard select of channel 3 is enabled, and if "0", disabled.
• ADHENC12 (bit 4)
This bit enables or disables hard select A/D conversion on channel 12.
If this bit is "1", the hard select of channel 12 is enabled, and if "0", disabled.
• ADHENC13 (bit 5)
This bit enables or disables hard select A/D conversion on channel 13.
If this bit is "1", the hard select of channel 13 is enabled, and if "0", disabled.
• ADHENC14 (bit 6)
This bit enables or disables hard select A/D conversion on channel 14.
If this bit is "1", the hard select of channel 14 is enabled, and if "0", disabled.
• ADHENC15 (bit 7)
This bit enables or disables hard select A/D conversion on channel 15.
If this bit is "1", the hard select of channel 15 is enabled, and if "0", disabled.
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