MSM54C865 Datasheet, PDF (37/44 Pages) OKI electronic componets – 65,536-Word X 8-Bit Multiport DRAM

¡ Semiconductor
MSM54C865
RAM PORT OPERATION
Fast Page Mode
Fast page mode allows data to be transferred into or out of multiple column locations of the
same row by performing multiple CAS cycle during a single activity for a period up to 100m
seconds. For the initial fast page mode access, the output data is valid after the specified access
times from RAS, CAS, column address and DT/OE.
For all subsequent fast page mode read operations, the output data is valid after the specified
access times from CAS, column address and DT/OE. When the write-per-bit function is enabled,
the mask data latched at the falling edge of RAS is maintained throughout the fast page mode
write or read or read modify write cycle.
RAS-Only Refresh
The data in the DRAM requires periodic refreshing to prevent data loss. Refreshing is
accomplished by performing a memory cycle at each of the 256 rows in the DRAM array within
the specified 4 ms refresh period.
Although any normal memory cycle will perform the refresh operation, this function is most
easily accomplished with "RAS-Only" cycle.
Block Write
Block write allows for the data in the color register to be written into 4 consecutive column
address locations starting from a selectively controlled on an I/O basis and column mask
capability is also available.
Block write cycle is performed by holding CAS, DT/OE "high" and DSF "low" at the falling edge
of RAS and by holding DSF "high" at the falling edge of CAS. The state of the WB/WE input at
the falling edge of RAS determines whether or not the I/O data mask is enabled (WB/WE must
be "low" to enable the I/O mask or "high" to disable mask). At the falling edge of RAS, a valid
row address and I/O mask data are also specified. At the falling edge of CAS, the starting column
address location and column mask data must be provided. During a block write cycle, the 2 least
significant column address locations (A0C, A1C) are internally controlled and only the 6 most
significant column addresses (A2C - A7C) are latched at the falling edge of CAS.
37/44