ML9051G Datasheet, PDF (24/74 Pages) OKI electronic componets – 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

OKI Semiconductor
PEDL9051G-01
ML9051G
• Line address circuit
The line address circuit is used for specifying the line address corresponding to the common output when
displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is
specified using the display start line address set command (COM0 output in the forward display state of the
common output, and COM47 output in the reverse display state). The display area is 48 lines in the direction of
increasing line address from the specified display start line address. When the indicator–dedicated common output
pin (COMS) is selected, data in Line Address 40 H = page 8 and bit 0 is displayed irrespective of the display start
line address. COMS selection is 49th in order.
It is possible to carry out screen scrolling by dynamically changing the line address using the display start line
address set command.
• Display data latch circuit
The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being
output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the
display ON/OFF control the data in this latch, the data in the display data RAM will not be changed.
Oscillator Circuit
This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = “H”
and also CLS = “H”. The oscillations will be stopped when CLS = “L”, and the display clock has to be input to the
CL pin.
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