MSM7712 Datasheet, PDF (16/20 Pages) OKI electronic componets – Wireless LAN Baseband Controller

s MSM7712 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
AC Characteristics
Processor Interface
The MSM7712 is designed to operate with the V80C86, V33, V53A, and 80C186 processors. Refer to the
appropriate processor data sheets for detailed information.
Host Interface
The MSM7712 meets the timing requirements of the PCMCIA interface. Wait states are used to provide
the access times to the shared RAM when required.
Shared Memory Interface
Shared Memory Timing ^[1]
Parameter
Description
t_S(RCE)
t_H(RCE)
t_RCE
t_S(D-CE)
t_ACC
t_H(RCE-D)
t_H(CYC)
Setup time of address, WR strobe and data output to RCE asserted
Hold time of address, WR strobe and data output to RCE deasserted
RCE low period (with 16/32 MHz SCK)
Setup time of read data to RCE deasserted
RAM access time Tce -Ts (d-rce)
Hold time of read data to RCE deasserted
Hold time before data bus driven low
1. RCK at 16 MHz.
Min.
Typ.
Max.
Unit
20
-
-
10
-
-
85
-
-
10
-
-
ns
75
-
-
0
-
-
50
-
70
RA[], RWRN
RCEHN, RCELN
RD[], READ
T_S(RCE)
T_RCE
T_B(RCE)
T_H(CYC)
T_S(D-RCE)
T_H(RCE-D)
RD[], WRITE
Figure 6. Shared Memory Timing
The shared memory cycle time is 2 RCK clock periods. When the memory interface is not active the data
bus RD[15:0] is output (low). This ensures the shared memory data bus does not float and consume
power.
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