MS8104160A Datasheet, PDF (11/24 Pages) OKI electronic componets – Dual FIFO (262,214 Words × 8 Bits) × 2

OKI Semiconductor
FEDS8104160A-01
MS8104160A
Read Operation Cycle (MODE2=V_SS)
The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2.
Port1 read operation is accomplished by cycling SRCK, and holding RE1 and OE1 high after the read address
pointer reset operation or RSTR1.
Each read operation, which begins after RSTR1, must contain at least 140 active read cycles, i.e. SRCK cycles
while RE1 and OE1 are high.
These operations are the same for Port1 and Port2.
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output.
WE1, 2
H
H
L
L
IE1, 2
H
L
X
L
Internal Write address pointer
Incremented
Halted
Data output
Output
High impedance
Output
High impedance
Read Operation Cycle (MODE2=V_CC)
The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2.
Port1 read operation is accomplished by cycling SRCK, and holding RE1 and OE1 low after the read address
pointer reset operation or RSTR1.
Each read operation, which begins after RSTR1, must contain at least 140 active read cycles, i.e. SRCK cycles
while RE1 and OE1 are low.
These operations are the same for Port1 and Port2.
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output.
RE1,2
L
L
H
H
OE1,2
L
H
L
H
Internal Write address pointer
Incremented
Halted
Data output
Output
High impedance
Output
High impedance
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