MSM9554 Datasheet, PDF (1/7 Pages) OKI electronic componets – LSI Devices for FM Multiplex Data Demodulation

¡ _¡ Semicond_Suc_etor_miconductor
MSM9554/MSM9555
LSI Devices for FM Multiplex Data Demodulation
MSM9554/MSM9555
GENERAL DESCRIPTION
The MSM9554 and MSM9555 are LSI devices which demodulate FM character multiplex signals in
the DARC (DAta Radio Channel)^*1 format to acquire digital data. The MSM9554 and MSM9555
operate on 5V and 3V, respectively. In the DARC format, baseband signals at ordinary FM
broadcasting frequencies are multiplexed with 16k-bps digital data which are L-MSK-modulated at
76kHz.
Each of the MSM9554 and MSM9555 has a bandpass filter consisting of SCF, frame synchroniza-
tion circuit, and error correction circuit, on a single chip.
So, a system for acquisition of digital data can be easily constructed by externally mounting an FM
receiver tuner, microcontroller for control, and memory for temporary storage of data.
The MSM9554 and MSM9555 have a simple configuration, and are equipped with only necessary
functions. By making changes to software for the external microcontroller, the MSM9554 and
MSM9555 can meet the various requirements of FM multiplex broadcasting services which will be
offered in future.
These devices are best suited to the car radios and car navigation systems supporting VICSs (Vehicle
Information and Communication System)^*2 that have been serviced since Aprit, 1996.
*1 DARC is a registered trademark of NHK ENGINEERING SERVICES, INC.
Note that a contract needs to be made with NHK Engineering Service if a manufacturer produces/
sells electronic equipment utilizing the DARC technology.
*2 If samples or detail documents are to be provided, contracts with VICS center are reqired
beforehand.
FEATURES
• Built-in discrambler supporting VICS
• Pin compatible with MSM9552/MSM9553
• Built-in bandpass filter (SCF)
• Built-in timer internal to block
• Built-in block synchronization circuit and frame synchronization circuit
• Setting of the number of synchronization protecting stages
• Regeneration of data clocks by digital PLL
• 1T delay detection
• Built-in error correction circuit
• Built-in layer 4 and layer 2 CRC check circuit
• Microcontroller parallel interface
• Clock output for external devices (64kHz to 8.192MHz selectable)
• International standard frame format
• Power source: 5V (MSM9554), 3V (MSM9555)
• Package
44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9554GS-2K/MSM9555GS-2K)
1