MSM6636 Datasheet, PDF (1/11 Pages) OKI electronic componets – SAE-J1850 Communication Protocol Conformity Transmission Controller for Automotive LAN

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MSM6636
MSM6636
SAE-J1850 Communication Protocol Conformity Transmission Controller for Automo-
tive LAN
GENERAL DESCRIPTION
The MSM6636 is a transmission controller for automotive LAN based on data communication
protocol SAE-J1850. This LSI can realize a data bus topology bus LAN system with a PWM bit
encoding method (41.6 K bps). In addition to a protocol control circuit, MSM6636 has an enclosed
quartz oscillation circuit, host CPU interface (clock synchronous serial / UART), a transmit/
receive buffer, and a bus receiver circuit that decreases the burden on the host CPU.
FEATURES
• Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued
August 12, 1991)
• CSMA/CD (Carrier-sense multiple access with collision detection)
• Internal transmit buffer (1 frame) and receive buffer (2 frames)
• Bit encoding: PWM (Pulse Width Modulation)
• Transmission Speed: 41.6K bps
• Multi-address setting with physical addressing: 1 type / functional addressing: 15 types
• Address filter function by multi-addressing (broadcasting possible)
• Automatic retransmission function by arbitration loss and non ACK
• 3 types of in-frame response support:
q Single-byte response from a single recipient
w Multi-byte response from a single recipient (with CRC code)
e Single-byte response from multiple recipients (ID response as ACK)
• Error detection by cyclic redundancy check (CRC)
• Various communication error detections
• Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function
• Host CPU interface is LSB first / serial, 4 modes supported
q Clock synchronous serial (no parity)
Normal mode: 8-bit data
MPC Mode: 8-bit data + MPC bit (1: address / 0: data select bit)
w UART (yes/no parity selectable)
Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit
MPC mode: 1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit
• Sleep Function
Low current consumption mode by oscillation stop (IDS Max < 50µA)
SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus
• Available package 18pin DIP, 18 pin QFJ (PLCC) and 24pin SOP.
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