MS82V32520 Datasheet, PDF (1/42 Pages) OKI electronic componets – 524,288-Word × 32-Bit × 2-Bank FIFO-SGRAM

PEDS82V32520-01
1_{Semiconductor}
MS82V32520
524,288-Word × 32-Bit × 2-Bank FIFO-SGRAM
This version: Jul. 2001
Preliminary
GENERAL DESCRIPTION
The MS82V32520 is a 32-Mbit system clock synchronous dynamic random access memory. In addition to the
conventional random read/write access function, the MS82V32520 provides the automatic row address increment
function and automatic bank switching function. Therefore, if once the row and column addresses are set,
continuous serial accesses are possible while banks are automatically switched till input of the Precharge
command. The MS82V32520 is ideal for digital camera and TV buffer memory applications.
FEATURES
• 524,288 words × 32 bits × 2 banks memory (2,048 rows × 256 columns × 32 bits × 2 banks)
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible inputs and outputs
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (2, 3)
• Automatic row address increment function and automatic bank switching function
• Power Down operation and Clock Suspend operation
• 4,096 refresh cycles/64 ms
• Auto refresh and self refresh capability
• Package:
86-pin 400 mil plastic TSOP (II) (TSOP (2) 86-P-400-0.50-K) (Product : MS82V32520-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Family
MS82V32520-75
MS82V32520-8
MS82V32520-10
Max. Operating Frequency
133 MHz
125 MHz
100 MHz
Access Time
5.5 ns
6 ns
7 ns
Package
86-pin Plastic TSOP (II) (400 mil)
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