MS81V05200 Datasheet, PDF (1/25 Pages) OKI electronic componets – (583,680-word × 10-bit) FIFO memory

FEDS81V05200-01
1_{Semiconductor}
MS81V05200
(583,680-word × 10-bit) FIFO memory
This version: Jun. 2001
GENERAL DESCRIPTION
The MS81V05200 is a 5.6Mb FIFO (First-In First-Out) memory designed for 583,680-words × 10-bit high-speed
asynchronous read/write operation.
The MS81V05200 is best suited for a field memory for digital TVs or LCD panels which require high-speed, large
memory, and is not designed for high end use in professional graphics systems, which require long term picture
storage and data storage.
The MS81V05200 is provided with independent control clocks to support asynchronous read and write operations.
Different clock rates are also supported, which allow alternate data rates between write and read data streams.
The first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write
operation is enabled after 1600 ns + 4 cycles from write reset. Thereafter, the high-speed read/write operation is
possible every cycle time. Additionally, a write mask function by IE pin and a read-data skipping function by OE
pin implement image data processing easily.
The MS81V05200 provides high speed FIFO (First-in First-out) operation without external refreshing:
MS81V05200 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.
The MS81V05200’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by
reset timing. The delay length and the number of read delay clocks between write and read, is determined by
externally controlled write and read reset timings. The MS81V05200 uses a thin and small 70-pin plastic TSOP.
FEATURES
• 583,680 words × 10 bits
• Fast FIFO (First-In First-Out) operation: 13 ns cycle time
• Self refresh (No refresh control is required)
• High speed asynchronous read/write operation
• Variable length delay bit (600 to 583,680)
• Single power supply: 3.3 V ±0.3 V
• Package:
70-pin plastic TSOP TYPE II (TSOP(2) 70-P-400-0.5-K)
PARAMETERS
Parameter
Access Time
Read/Write
Cycle Time
Operation Current
Standby Current
Symbol
t_AC
t_SWC
t_SRC
I_CC1
I_CC2
MS81V05200-TA
8 ns
13 ns
200 mA
6 mA
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