PMP5501V Datasheet, PDF (9/14 Pages) NXP Semiconductors – PNP/PNP matched double transistors

NXP Semiconductors
PMP5501V; PMP5501G; PMP5501Y
PNP/PNP matched double transistors
10. Packing information
Table 9. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.^[1]
Type number Package Description
Packing quantity
3000 4000 8000 10000
PMP5501V SOT666 2 mm pitch, 8 mm tape and reel
-
-
-315 -
4 mm pitch, 8 mm tape and reel
-
-115 -
-
PMP5501G SOT353 4 mm pitch, 8 mm tape and reel
-115 -
-
-135
PMP5501Y SOT363 4 mm pitch, 8 mm tape and reel; T1 ^[2] -115 -
-
-135
4 mm pitch, 8 mm tape and reel; T2 ^[3] -125 -
-
-165
[1] For further information and the availability of packing methods, see Section 14.
[2] T1: normal taping
[3] T2: reverse taping
11. Soldering
2.75
2.45
2.1
1.6
0.538
2 1.7 1.075
0.55
(2×)
0.4
(6×) ^{0.25 0.3}
(2×) (2×)
1.7
0.45
0.6
(4×)
(2×)
0.5
0.65
(4×)
(2×)
0.325 0.375
(4×) (4×)
Reflow soldering is the only recommended soldering method.
Fig 14. Reflow soldering footprint SOT666
solder lands
placement area
solder paste
occupied area
Dimensions in mm
sot666_fr
PMP5501V_G_Y_3
Product data sheet
Rev. 03 — 28 August 2009
© NXP B.V. 2009. All rights reserved.
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