74AVC2T45DP Datasheet, PDF (9/27 Pages) NXP Semiconductors – Dual-bit, dual-supply voltage level translator/transceiver; 3-state

NXP Semiconductors
74AVC2T45
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
11. Dynamic characteristics
Table 9. Typical dynamic characteristics at V_CC(A) = 0.8 V and T_amb = 25 C ^[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
0.8 V
1.2 V
V_CC(B)
1.5 V 1.8 V
2.5 V
Unit
3.3 V
t_pd
propagation delay A to B
B to A
15.5
8.1
7.6
7.7
8.4
9.2 ns
15.5
12.7
12.3
12.2
12.0
11.8 ns
t_dis
disable time
DIR to A
DIR to B
12.2
12.2
12.2
12.2
12.2
12.2 ns
11.7
7.9
7.6
8.2
8.7
10.2 ns
t_en
enable time
DIR to A
DIR to B
27.2
20.6
19.9
20.4
20.7
22.0 ns
27.7
20.3
19.8
19.9
20.6
21.4 ns
[1] t_pd is the same as t_PLH and t_PHL; t_dis is the same as t_PLZ and t_PHZ; t_en is the same as t_PZL and t_PZH.
t_en is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 10. Typical dynamic characteristics at V_CC(B) = 0.8 V and T_amb = 25 C ^[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
0.8 V
1.2 V
V_CC(A)
1.5 V 1.8 V
2.5 V
Unit
3.3 V
t_pd
propagation delay A to B
B to A
15.5
12.7
12.3
12.2
12.0
11.8 ns
15.5
8.1
7.6
7.7
8.4
9.2 ns
t_dis
disable time
DIR to A
DIR to B
12.2
4.9
3.8
3.7
2.8
3.4 ns
11.7
9.2
9.0
8.8
8.7
8.6 ns
t_en
enable time
DIR to A
DIR to B
27.2
17.3
16.6
16.5
17.1
17.8 ns
27.7
17.6
16.1
15.9
14.8
15.2 ns
[1] t_pd is the same as t_PLH and t_PHL; t_dis is the same as t_PLZ and t_PHZ; t_en is the same as t_PZL and t_PZH.
t_en is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 11. Typical power dissipation capacitance at V_CC(A) = V_CC(B) and T_amb = 25 C ^[1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
0.8 V
1.2 V
V_CC(A) and V_CC(B)
1.5 V 1.8 V
C_PD
power dissipation A port: (direction A to B);
1
2
2
2
capacitance
B port: (direction B to A)
A port: (direction B to A); 9
B port: (direction A to B)
11
11
12
2.5 V
2
14
[1] C_PD is used to determine the dynamic power dissipation (P_D in W).
P_D = C_PD  V_CC2  f_i  N + (C_L  V_CC2  f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = load capacitance in pF;
V_CC = supply voltage in V;
N = number of inputs switching;
(C_L  V_CC2  f_o) = sum of the outputs.
[2] f_i = 10 MHz; V_I = GND to V_CC; t_r = t_f = 1 ns; C_L = 0 pF; R_L =  .
Unit
3.3 V
2 pF
17 pF
74AVC2T45
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 8 February 2013
© NXP B.V. 2013. All rights reserved.
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