74AUP1G09 Datasheet, PDF(9/15 Page) NXP Semiconductors – Low-power 2-input AND gate with open-drain

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74AUP1G09 Datasheet, PDF (9/15 Pages) NXP Semiconductors – Low-power 2-input AND gate with open-drain

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NXP Semiconductors

74AUP1G09

Low-power 2-input AND gate with open-drain

VCC

VEXT

DUT

5 kâ¦

001aac521

Fig 8.

Test data is given in Table 10.

Deï¬nitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Test circuit for measuring switching times

Table 10. Test data

Supply voltage

Load

VCC

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

RL[1]

5 kâ¦ or 1 Mâ¦

VEXT

tPLH, tPHL

open

[1] For measuring enable and disable times RL = 5 kâ¦.

For measuring propagation delays, set-up and hold times, and pulse width, RL = 1 Mâ¦.

tPZH, tPHZ

GND

tPZL, tPLZ

2VCC

74AUP1G09_1

Product data sheet

Rev. 01 â 15 January 2009

9 of 15

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