TJA1041A Datasheet, PDF(8/25 Page) NXP Semiconductors

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TJA1041A Datasheet, PDF (8/25 Pages) NXP Semiconductors – High speed CAN transceiver

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NXP Semiconductors

TJA1041A

High-speed CAN transceiver

Table 5. Accessing internal ï¬ags via pin ERR â¦continued

Internal

ï¬ag

Flag is available on pin ERR[1]

Flag is cleared

wake-up

source

in Normal mode (before the fourth

on leaving Normal mode, or by setting

dominant to recessive edge on pin TXD[2]) the pwon ï¬ag

bus failure in Normal mode (after the fourth dominant on reentering Normal mode

to recessive edge on pin TXD[2])

local failure in Pwon/Listen-only mode (coming from

Normal mode)

on entering Normal mode or when RXD

is dominant while TXD is recessive

(provided that all local failures are

resolved)

[1] Pin ERR is an active-LOW output, so a LOW-level indicates a set ï¬ag and a HIGH-level indicates a cleared

ï¬ag. Allow pin ERR to stabilize for at least 8 Âµs after changing operating modes.

[2] Allow for a TXD dominant time of at least 4 Âµs per dominant-recessive cycle.

7.2.1

UVNOM ï¬ag

UVNOM is the VCC and VI/O undervoltage detection ï¬ag. The ï¬ag is set when the voltage

on pin VCC drops below VCC(sleep) for longer than tUV(VCC) or when the voltage on pin VI/O

drops below VI/O(sleep) for longer than tUV(VI/O). When the UVNOM ï¬ag is set, the transceiver

will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage

regulators connected to pin INH are disabled, avoiding the extra power consumption in

case of a short circuit condition. After a waiting time (ï¬xed by the same timers used for

setting UVNOM) any wake-up request or setting of the pwon ï¬ag will clear UVNOM and the

timers, allowing the voltage regulators to be reactivated at least until UVNOM is set again.

7.2.2

UVBAT ï¬ag

UVBAT is the VBAT undervoltage detection ï¬ag. The ï¬ag is set when the voltage on

pin VBAT drops below VBAT(stb). When UVBAT is set, the transceiver will try to enter

Standby mode to save power and not disturb the bus. UVBAT is cleared when the voltage

on pin VBAT has recovered. The transceiver will then return to the operating mode

determined by the logic state of pins STB and EN.

7.2.3 Pwon ï¬ag

Pwon is the VBAT power-on ï¬ag. This ï¬ag is set when the voltage on pin VBAT has

recovered after it dropped below VBAT(pwon), particularly after the transceiver was

disconnected from the battery. By setting the pwon ï¬ag, the UVNOM ï¬ag and timers are

cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage

regulator connected to pin INH is activated when the node is reconnected to the battery. In

Pwon/Listen-only mode the pwon ï¬ag can be made available on pin ERR. The ï¬ag is

cleared when the transceiver enters Normal mode.

7.2.4 Wake-up ï¬ag

The wake-up ï¬ag is set when the transceiver detects a local or a remote wake-up request.

A local wake-up request is detected when a logic state change on pin WAKE remains

stable for at least twake. A remote wake-up request is detected after two bus dominant

states of at least tBUSdom (with each dominant state followed by a recessive state of at

least tBUSrec). The wake-up ï¬ag can only be set in Standby mode, Go-to-sleep command

mode or Sleep mode. Setting of the ï¬ag is blocked during the UVNOM ï¬ag waiting time. By

setting the wake-up ï¬ag, the UVNOM ï¬ag and timers are cleared. The wake-up ï¬ag is

TJA1041A_4

Product data sheet

Rev. 04 â 29 July 2008

8 of 25

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