PESD1USB3SZ Datasheet, PDF (8/19 Pages) NXP Semiconductors – ESD protection for differential data lines

NXP Semiconductors
PESDxUSB3S series
ESD protection for differential data lines
25
I
(A)
20
aaa-021326
0
I
(A)
-5
aaa-021327
15
-10
10
-15
5
-20
0
0
5
10
15
20
25
V_CL (V)
Fig 8.
Transmission Line Pulse (TLP) = 100 ns
Dynamic resistance with positive clamping;
typical values
25
I
(A)
20
aaa-021328
-25
-25
-20
-15
-10
-5
0
V_CL (V)
Fig 9.
Transmission Line Pulse (TLP) = 100 ns
Dynamic resistance with negative clamping;
typical values
0
I
(A)
-5
aaa-021329
15
-10
10
-15
5
-20
0
0
5
10
15
20
25
V_CL (V)
Transmission Line Pulse (TLP) = 5 ns
Fig 10. Dynamic resistance with positive clamping;
typical values
-25
-25
-20
-15
-10
-5
0
V_CL (V)
Transmission Line Pulse (TLP) = 5 ns
Fig 11. Dynamic resistance with negative clamping;
typical values
The device uses an advanced clamping structure showing a negative dynamic resistance.
This snap-back behavior strongly reduces the clamping voltage to the system behind the
ESD protection during an ESD event. Do not connect unlimited DC current sources to the
data lines to avoid keeping the ESD protection device in snap-back state after exceeding
breakdown voltage (due to an ESD pulse for instance).
PESDXUSB3S_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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