PCA9646 Datasheet, PDF (8/22 Pages) NXP Semiconductors – Buffered 4-channel 2-wire bus switch

NXP Semiconductors
PCA9646
Buffered 4-channel 2-wire bus switch
Table 4. Characteristics …continued
T_amb = 40 C to +85 C; voltages are specified with respect to ground (V_SS); V_DD = 5.5 V unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
RESET
V_IH
HIGH-level input voltage
V_IL
LOW-level input voltage
V_hys
hysteresis voltage
I_LI
input leakage current
t_w(rst)L
LOW-level reset time
t_rst
reset time
t_POR
power-on reset pulse time
Address pins (A0, A1, A2)
V_DD = 2.7 V
V_DD = 5.5 V
V_DD = 2.7 V
V_DD = 5.5 V
V_DD = 2.7 V
V_DD = 5.5 V
pin at V_DD or V_SS
V_I < V_IL
RESET pin; from V_I > V_IH
RESET pin; from V_I > V_IH
2.0
-
-
V
4.8
-
-
V
-
-
650
mV
-
-
900
mV
100
-
-
mV
200
-
-
mV
1
-
+1
A
[2] _-
25
-
ns
-
250
500
ns
-
250
500
ns
V_IH
HIGH-level input voltage
V_IL
LOW-level input voltage
I_LI
input leakage current
Timing characteristics (Figure 8)
V_DD = 2.7 V
V_DD = 5.5 V
V_DD = 2.7 V
V_DD = 5.5 V
pin at V_DD or V_SS
1.7
-
-
V
3.5
-
-
V
-
-
0.7
V
-
-
1.5
V
1
-
+1
A
t_d
delay time
t_f
fall time
R_PU = 200 ; V_DD = 2.7 V
R_PU = 200 ; V_DD = 5.5 V
R_PU = 200 
-
100
-
ns
-
70
-
ns
-
16
-
ns
[1] Supply voltage dependent; refer to graphs (Figure 9 through Figure 12) for typical trend.
[2] Guaranteed by design, not subject to test.
V_I2C-bus
Fig 8. Timing diagram
70 % V_DD
V_IL
t_d
30 % V_DD
SDx, SCx input
SDx, SCx output
t_f
time
002aaf438
PCA9646
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 March 2011
© NXP B.V. 2011. All rights reserved.
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