PCA9633_08 Datasheet, PDF (8/43 Pages) NXP Semiconductors – 4-bit Fm+ I2C-bus LED driver

NXP Semiconductors
PCA9633
4-bit Fm+ I²C-bus LED driver
7. Functional description
Refer to Figure 1 “Block diagram of PCA9633”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 128 possible programmable addresses using the 7 hardware
address pins. Two of these addresses, Software Reset and LED All Call, cannot be used
because their default power-up state is ON, leaving a maximum of 126 addresses. Using
other reserved addresses, as well as any other subcall address, will reduce the total
number of possible addresses even further.
7.1.1 Regular I²C-bus slave address
The I²C-bus slave address of the PCA9633 is shown in Figure 8. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW (10-pin and 16-pin versions).
Remark: Using reserved I²C-bus addresses will interfere with other devices, but only if the
devices are on the bus and/or the bus will be open to other I²C-bus systems at some later
date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9633 treats them like any other address. The
LED All Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
• PCA9633 LED All Call address (1110 000) and Software Reset (0000 0110) which
are active on start-up
• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
• ‘reserved for future use’ I²C-bus addresses (0000 011, 1111 1XX)
• slave devices that use the 10-bit addressing scheme (1111 0XX)
• slave devices that are designed to respond to the General Call address (0000 000)
• High-speed mode (Hs-mode) master code (0000 1XX).
slave address
1 1 0 0 0 1 0 R/W
fixed
002aab318
a. 8-pin version
Fig 8. Slave address
slave address
1 1 0 0 0 A1 A0 R/W
fixed
hardware
selectable
002aab295
b. 10-pin version
slave address
A6 A5 A4 A3 A2 A1 A0 R/W
hardware selectable
002aab319
c. 16-pin version
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
PCA9633_5
Product data sheet
Rev. 05 — 25 July 2008
© NXP B.V. 2008. All rights reserved.
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