PCA9535 Datasheet, PDF (8/32 Pages) NXP Semiconductors – 16-bit I2C and SMBus, low power I/O port with interrupt

NXP Semiconductors
PCA9535; PCA9535C
16-bit I²C-bus and SMBus, low power I/O port with interrupt
6.2.5 Registers 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
Table 11.
Bit
Symbol
Default
Configuration port 0 register
7
6
5
C0.7
C0.6
C0.5
1
1
1
4
C0.4
1
3
C0.3
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
Table 12.
Bit
Symbol
Default
Configuration port 1 register
7
6
5
C1.7
C1.6
C1.5
1
1
1
4
C1.4
1
3
C1.3
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
6.3 Power-on reset
When power is applied to V_DD, an internal power-on reset holds the PCA9535/PCA9535C
in a reset condition until V_DD has reached V_POR. At that point, the reset condition is
released and the PCA9535/PCA9535C registers and SMBus state machine will initialize
to their default states. Thereafter, V_DD must be lowered below 0.2 V to reset the device.
For a power reset cycle, V_DD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 I/O port
When an I/O is configured as an input on PCA9535, FETs Q1 and Q2 are off, creating a
high impedance input. The input voltage may be raised above V_DD to a maximum of 5.5 V.
In the case of PCA9535C, FET Q1 has been removed and the open-drain FET Q2 will
function the same as PCA9535.
If the I/O is configured as an output, then on PCA9535 either Q1 or Q2 is on, depending
on the state of the Output Port register. Care should be exercised if an external voltage is
applied to an I/O configured as an output because of the low-impedance path that exists
between the pin and either V_DD or V_SS.
PCA9535_PCA9535C_3
Product data sheet
Rev. 03 — 4 October 2007
© NXP B.V. 2007. All rights reserved.
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