PCA2125 Datasheet, PDF (8/40 Pages) NXP Semiconductors – SPI Real time clock / calendar

NXP Semiconductors
PCA2125
SPI Real time clock / calendar
Power on reset override available to be set
24 hour mode is selected
6.2.1 Power-On Reset (POR) override
The power on reset duration is directly related to the crystal oscillator start-up time. Due to
the long start-up times experienced by these types of circuits, a mechanism has been built
in to disable the POR and hence speed up on-board test of the device (see Figure 5).
osc stopped
OSCILLATOR _{0 = stopped, 1 = running}
SDI
POR
OVERRIDE 0 = override inactive
1 = override active
CE
CLEAR
reset
POR_OVRD 0 = clear override mode
REGISTER 1 = override possible
001aaf898
Fig 5. Reset system.
The setting of this mode requires that the ‘POR ovrd’ register be set to ‘1’ and that the
SPI bus pins, SDI and CE, be toggled in a specific order as shown in Figure 6. All timings
are required minimums.
Once the override mode has been entered, the device immediately stops being reset and
set-up operation may commence i.e. entry into the external clock test mode via the
SPI bus access. The override mode may be cleared by writing a logic 0 to ‘POR ovrd’.
‘POR ovrd’ must be set to logic 1 before re-entry into the override mode is possible.
Setting ‘POR ovrd’ to logic 0 during normal operation has no effect except to prevent
accidental entry into the POR override mode. This is the recommended setting.
SDI
CE
reset
override
minimum 500 ns
minimum 500 ns
Fig 6. POR override sequence.
minimum 2000 ns
POR override set at this time
001aaf900
PCA2125_00
Preliminary data sheet
Rev. 00.11 — 30 January 2007
© NXP B.V. 2007. All rights reserved.
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