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DAC1403D160 Datasheet, PDF (8/19 Pages) NXP Semiconductors – Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
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NXP Semiconductors
DAC1403D160
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
10. Characteristics
Table 5. Characteristics
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = −40 °C to +85 °C; typical values measured at
VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in
Figure 10; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
Supplies
VCCD
VCCA
ICCD
ICCA
Ptot
digital supply voltage
analog supply voltage
digital supply current
analog supply current
total power dissipation
Clock inputs (CLK and CLKN)
fclk = 80 MHz;
fIOUT = fQOUT = 5 MHz
3.0
3.3 3.6
V
3.0
3.3 3.6
V
-
55
65
mA
-
73
85
mA
-
422 540
mW
VI(cm)
common-mode input
voltage
-
1.65 -
V
Vi(dif)(p-p)
peak-to-peak differential
input voltage
-
1.0 -
V
Analog outputs (IOUT, IOUTN, QOUT and QOUTN)
IO(fs)
full-scale output current differential outputs
Ro
output resistance
Co
output capacitance
Digital inputs (I0 to I13, Q0 to Q13 and GAPD)
4
[1] -
[1] -
-
20
mA
150 -
kΩ
3
-
pF
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IIL
LOW-level input current
IIH
HIGH-level input current
Reference voltage output (GAPOUT)
VIL = 0.3 VCCD
VIH = 0.7 VCCD
DGND -
0.7 VCCD -
-
5
-
5
0.3 VCCD V
VCCD
V
-
µA
-
µA
VGAPOUT
IGAPOUT
∆VGAPOUT
voltage on pin GAPOUT
current on pin GAPOUT
voltage variation on pin
GAPOUT
external voltage
-
1.31 -
V
-
1
-
µA
-
±133 -
ppm/°C
Clock timing inputs (CLK and CLKN)
fclk
clock frequency
tw(clk)H
HIGH clock pulse width
tw(clk)L
LOW clock pulse width
Input timing (I0 to I13 and Q0 to Q13); see Figure 5
-
-
80
MHz
5
-
-
ns
5
-
-
ns
th(i)
input hold time
tsu(i)
input set-up time
Output timing (IOUT, IOUTN, QOUT, QOutN)
1.1
-
−1.5
-
3.4
ns
+0.7
ns
ts
settling time
to = ± 0.5 LSB
[1] -
43
-
ns
DAC1403D160_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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