PCF8566 Datasheet, PDF (7/48 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
V_DD
R
≤
t_rise
2 C_bus
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
V_SS
V_DD
V_LCD
5
SDA ₁
12
17 to 40 24 segment drives
SCL ₂
OSC
6
7
PCF8566
13 to 16
8 9 10 11
4 backplanes
A0 A1 A2 SA0 V_SS
Fig 4. Typical system configuration
LCD PANEL
(up to 96
elements)
mgg385
7.1 Power-on reset
At power-on the PCF8566 resets to the following starting conditions:
• All backplane outputs are set to V_DD
• All segment outputs are set to V_DD
• Drive mode 1:4 multiplex with ¹â„₃ bias is selected
• Blinking is switched off
• Input and output bank selectors are reset (as defined in Table 8)
• The I²C-bus interface is initialized
• The data pointer and the subaddress counter are cleared
Do not transfer data on the I²C-bus after a power-on for at least 1 ms to allow the reset
action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (V_oper) is obtained from V_DD − V_LCD. The LCD voltage may be
temperature compensated externally through the V_LCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between V_DD and V_LCD. The center resistor can be
switched out of the circuit to provide a ¹â„₂ bias voltage level for the 1:2 multiplex
configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
mode-set commands from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
V_LCD and the resulting discrimination ratios (D), are given in Table 5.
PCF8566_7
Product data sheet
Rev. 07 — 25 February 2009
© NXP B.V. 2009. All rights reserved.
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