PCA9543A Datasheet, PDF (7/23 Pages) Texas Instruments – TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET

NXP Semiconductors
PCA9543A/43B/43C
2-channel I²C-bus switch with interrupt logic and reset
Remark: Two interrupts can be active at the same time.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of t_w(rst)L, the PCA9543A will reset
its registers and I²C-bus state machine and will deselect all channels. The RESET input
must be connected to V_DD through a pull-up resistor.
6.4 Power-on reset
When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA9543A in
a reset condition until V_DD has reached V_POR. At this point, the reset condition is released
and the PCA9543A registers and I²C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, V_DD must be
lowered below 0.2 V to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9543A are constructed such that the V_DD voltage can
be used to limit the maximum voltage that will be passed from one I²C-bus to another.
5.0
V_o(sw)
(V)
4.0
3.0
2.0
002aaa964
(1)
(2)
(3)
1.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V_DD (V)
(1) maximum
(2) typical
(3) minimum
Fig 8. Pass gate voltage versus supply voltage
Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 10 “Static characteristics” of this data
sheet). In order for the PCA9543A to act as a voltage translator, the V_o(sw) voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V_o(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
PCA9543A_43B_43C_5
Product data sheet
Rev. 05 — 17 November 2008
© NXP B.V. 2008. All rights reserved.
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