LPC54101J256BD64QL Datasheet, PDF (64/90 Pages) NXP Semiconductors – 32-bit ARM Cortex-M4/M0+ MCU; 104 kB SRAM; 512 kB flash, x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC

NXP Semiconductors
LPC5410x
32-bit ARM Cortex-M4/M0+ microcontroller
Table 27. SPI dynamic characteristics^[1]
T_amb = 40 C to 105 C; C_L = 30 pF balanced loading on all pins; SLEW = standard mode. Parameters sampled at the 50 %
level of the rising or falling edge.
Symbol Parameter
Conditions
Min
Max
Unit
t_DH
data hold time
CCLK = 1 MHz to 12 MHz
0
CCLK = 48 MHz to 60 MHz
0
-
ns
-
ns
CCLK = 96 MHz
0
-
ns
t_v(Q)
data output valid time CCLK = 1 MHz to 12 MHz
36
CCLK = 48 MHz to 60 MHz
21
61
ns
22
ns
CCLK = 96 MHz
20
21
ns
[1] Based on characterization; not tested in production.
SCK (CPOL = 0)
SCK (CPOL = 1)
T_cy(clk)
SSEL
MOSI (CPHA = 0)
t_v(Q)
DATA VALID (MSB)
MISO (CPHA = 0)
DATA VALID (MSB)
DATA VALID
t_DS
t_DH
DATA VALID
t_v(Q)
DATA VALID (LSB)
DATA VALID (LSB)
IDLE
IDLE
DATA VALID (MSB)
DATA VALID (MSB)
MOSI (CPHA = 1)
MISO (CPHA = 1)
t_v(Q)
DATA VALID (LSB)
DATA VALID (LSB)
DATA VALID
t_DS
t_DH
DATA VALID
t_v(Q)
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
IDLE
DATA VALID (MSB)
DATA VALID (MSB)
aaa-014969
T_cy(clk) = CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC5410x User manual.
Fig 21. SPI master timing
LPC5410x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.6 — 3 October 2016
© NXP B.V. 2016. All rights reserved.
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