PSMN2R5-30YL Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN2R5-30YL
N-channel TrenchMOS logic level FET
Table 6. Characteristics …continued
Symbol
Parameter
Conditions
Source-drain diode
V_SD
source-drain voltage I_S = 25 A; V_GS = 0 V; T_j = 25 °C; see
Figure 17
t_rr
reverse recovery time I_S = 20 A; dI_S/dt = -100 A/s; V_GS = 0 V;
Q_r
recovered charge
V_DS = 20 V
Min Typ Max Unit
-
0.88 1.2
V
-
39
-
ns
-
38
-
nC
003aac651
80
I_D
(A)
60
40
T_j = 150 °C
25 °C
20
0
0
1
2
3 _{VGS (V)} 4
I_D ¹⁶⁰ ₁₀
(A)
140 _4.5
120
100
003aac653
V_GS (V) = 3.2
3
80
2.8
60
40
2.6
20
2.4
2.2
0
0
2
4
6
8
10
V_DS (V)
Fig 5. Transfer characteristics: drain current as a
function of gate-source voltage; typical
values
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical
values
140
g_fs
(S)
120
100
80
60
40
0
003aac655
20
40
60 _{ID (A)} 80
9
R_DSon
(mΩ)
7
5
3
1
0
003aac658
V_GS (V) = 3.2
4.5
10
50
100 _{ID (A)} 150
Fig 7. Forward transconductance as a function of Fig 8. Drain-source on-state resistance as a
drain current; typical values
function of drain current; typical values
PSMN2R5-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
6 of 13