PCF2113X Datasheet, PDF (6/65 Pages) NXP Semiconductors – LCD controllers/drivers

NXP Semiconductors
PCF2113x
LCD controllers/drivers
Table 3.
Pin
8
9 to 16
17
18 to 25
-
-
26 to 50
-
-
51 to 75
-
Pin (LQFP100 package) or pad allocation table …continued
Pad
Symbol
Pin
Pad
11
V_LCDIN
92
101
12 to 19
R9 to R16
93
102
20
R18
94
103
21 to 28
C60 to C53 95
104
29
dummy pad 96
105
30
dummy pad 97
106
31 to 55
C52 to C28 98
107
56
dummy pad 99
108
57
dummy pad 100
109
58 to 82
C27 to C3
-
110
83
dummy pad -
-
Symbol
DB7
DB6
DB5
DB4
DB3/SA0
DB2
DB1
DB0
V_DD2
V_DD3
-
Table 4. Bonding pad dimensions
Pad
Size
Unit
Type
galvanic pure Au
Bump dimensions
(50 ± 6) × (90 ± 6) × (17.5 ± 5)
µm
Height difference in one die
<2
µm
Convex deformation
<5
µm
Pad size (aluminium)
62 × 100
µm
Passivation opening
36 × 76
µm
Pad pitch
−635.0
µm
Wafer thickness (excluding bumps)
380 ± 25
µm
Fab 1 ^[1]
Fab 2 ^[2]
Die size X
3.52
3.47
mm
Die size Y
3.36
3.31
mm
[1] Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer).
[2] Fab 2 identification starts with AXnnnn, where X represents a letter or a number and n represents a number
between 0 and 9 (6 inch wafer).
Table 5. Pin and bonding pad description
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type Pad
X (µm)
Y (µm)
Description
V_DD1
1
P
1
−1 345
−1 550
supply voltage 1 for all except V_LCD
generator
OSC
2
I
2
−1 155
−1 550
oscillator and external clock input
[1]
PD
3
I
3
−1 055
−1 550
power-down select input; for normal
operation PD is LOW
T3
-
I
4
−845
−1 550
test pad; open circuit and not user
accessible
T1
4
I
5
−765
−1 550
test pin; must be connected to V_SS1
T2
-
I
6
−665
−1 550
test pad; must be connected to V_SS1
V_SS1
5
P
7
−525
−1 550
ground 1 for all except V_LCD generator
PCF2113_FAM_4
Product data sheet
Rev. 04 — 4 March 2008
© NXP B.V. 2008. All rights reserved.
6 of 65