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LPC2210_08 Datasheet, PDF (6/50 Pages) NXP Semiconductors – 16/32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface
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Table 3.
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Ball allocation
Row Column
1
2
3
4
5
6
7
8
9
10
11
12
13
A P2.22/
D22
VDDA(1V8) P1.28/
TDI
P2.21/
D21
P2.18/
D18
P2.14/
D14
P1.29/
TCK
P2.11/
D11
P2.10/
D10
P2.7/D7 VDD(3V3) VDD(1V8) P2.4/D4
B VDD(3V3) P1.27/
TDO
XTAL2
VSSA(PLL) P2.19/
D19
P2.15/
D15
P2.12/
D12
P0.20/
VDD(3V3) P2.6/D6 VSS
MAT1.3/
SSEL1/
EINT3
P2.3/D3 VSS
C P0.21/
VSS
PWM5/
CAP1.3
XTAL1
VSSA
RESET
P2.16/
D16
P2.13/
D13
P0.19/
MAT1.2/
MOSI1/
CAP1.2
P2.9/D9
P2.5/D5
P2.2/D2
P2.1/D1
VDD(3V3)
D P0.24
P1.19/ P0.23
TRACEP
KT3
P0.22/ P2.20/ P2.17/ VSS
CAP0.0/ D20
D17
MAT0.0
P0.18/ P2.8/D8 P1.30/ VSS
CAP1.3/
TMS
MISO1/
MAT1.3
P1.20/
TRACES
YNC
P0.17/
CAP1.2/
SCK1/
MAT1.2
E P2.25/ P2.24/ P2.23/ VSS
D25
D24
D23
P0.16/
EINT0/
MAT0.2/
CAP0.2
P0.15/
RI1/
EINT2
P2.0/D0 P3.30/
BLS1
F P2.27/
P1.18/
VDDA(3V3) P2.26/
D27/
TRACEP
D26/
BOOT1 KT2
BOOT0
P3.31/
BLS0
P1.21/
VDD(3V3) VSS
PIPESTAT
0
G P2.29/
D29
P2.28/
D28
P2.30/ P2.31/
D30/AIN4 D31/AIN5
P0.14/
DCD1/
EINT1
P1.0/CS0 P3.0/A0 P1.1/OE
H P0.25
n.c.
P0.27/
AIN0/
CAP0.1/
MAT0.1
P1.17/
TRACEP
KT1
P0.13/
DTR1/
MAT1.1
P1.22/ P3.2/A2
PIPESTAT
1
P3.1/A1
J
P0.28/
VSS
AIN1/
CAP0.2/
MAT0.2
P3.29/
BLS2/
AIN6
P3.28/
BLS3/
AIN7
P3.3/A3
P1.23/ P0.11/
PIPESTAT CTS1/
2
CAP1.1
P0.12/
DSR1/
MAT1.0
K P3.27/WE P3.26/
CS1
VDD(3V3)
P3.22/
A22
P3.20/
A20
P0.1/
RXD0/
PWM3/
EINT0
P3.14/
A14
P1.25/ P3.11/
EXTIN0 A11
VDD(3V3) P0.10/
VSS
RTS1/
CAP1.0
P3.4/A4
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