GTL2007 Datasheet, PDF (6/20 Pages) NXP Semiconductors – 13-bit GTL to LVTTL translator with power good control

NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
Table 7. SMI signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input
10AI1/10AI2
9BI
L
L
L
H
H
L
H
H
Output
10BO1/10BO2
L
L
L
H
Table 8. PROCHOT signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
5BI/6BI
5A/6A (open-drain)
L
L
H
L^[2]
H
H
Output
7BO1/7BO2
H^[1]
L
H
[1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the
7BO1/7BO2 outputs.
[2] Open-drain input/output terminal is driven to logic LOW state by other driver.
Table 9. NMI signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
11BI
11A (open-drain)
L
H
L
L^[1]
H
L
Output
11BO
L
H
H
[1] Open-drain input/output terminal is driven to logic LOW state by other driver.
GTL2007_2
Product data sheet
Rev. 02 — 16 February 2007
© NXP B.V. 2007. All rights reserved.
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