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BUK762R6-40E Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel TrenchMOS standard level FET
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NXP Semiconductors
BUK762R6-40E
N-channel TrenchMOS standard level FET
Symbol
Parameter
Conditions
Ciss
input capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 15
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 30 V; RL = 1.2 Ω; VGS = 10 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf
fall time
LD
internal drain
from upper edge of drain mounting
inductance
base to center of die
LS
internal source
from source lead to source bonding
inductance
pad
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 25 V
400
ID
(A)
300
VGS(V) = 20
10 8
003aah109
16
RDSon
(mΩ)
12
Min Typ Max Unit
-
5350 7130 pF
-
1032 1240 pF
-
519 711 pF
-
29
-
ns
-
36
-
ns
-
62
-
ns
-
36
-
ns
-
2.5 -
nH
-
7.5 -
nH
-
0.81 1.2 V
-
39.5 -
ns
-
45.9 -
nC
003aah110
200
6
8
5.5
100
4
5
4.5
0
0
1
VDS(V)
2
0
0
5
10
15 VGS(V) 20
Fig. 6.
Tj = 25 °C; tp = 300 μs
Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7.
Drain-source on-state resistance as a function
of gate-source voltage; typical values
BUK762R6-40E
Product data sheet
All information provided in this document is subject to legal disclaimers.
13 July 2012
© NXP B.V. 2012. All rights reserved
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