PCF2127A Datasheet, PDF (59/80 Pages) NXP Semiconductors – Integrated RTC, TCXO and quartz crystal

NXP Semiconductors
PCF2127A
Integrated RTC, TCXO and quartz crystal
Table 59. I²C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
1
0
1
0
0
0
1
R/W
The R/W bit defines the direction of the following single or multiple byte data transfer (read
is logic 1, write is logic 0).
For the format and the timing of the START condition (S), the STOP condition (P), and the
acknowledge bit (A) refer to the I²C-bus specification Ref. 13 “UM10204” and the
characteristics table (Table 64). In the write mode a data transfer is terminated by sending
either a STOP condition or the START condition of the next data transfer.
acknowledge
from PCF2127A
acknowledge
from PCF2127A
acknowledge
from PCF2127A
S10100010A
A
slave address
write bit
register address
00h to 1Dh
Fig 42. Bus protocol, writing to registers
0 to n
data bytes
A P/S
START/
STOP
001aaj719
acknowledge
from PCF2127A
acknowledge
from PCF2127A
S10100010A
slave address
write bit
register address
00h to 1Dh
AP
STOP
set register
address
acknowledge
from PCF2127A
acknowledge
from master
no acknowledge
S10100011A
DATA BYTE
read register
A
LAST DATA BYTE
AP
data
slave address
read bit
0 to n data bytes
001aaj721
Fig 43. Bus protocol, reading from registers
PCF2127A_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 May 2010
© NXP B.V. 2010. All rights reserved.
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