PCF8537 Datasheet, PDF (58/82 Pages) NXP Semiconductors – Industrial LCD driver for multiplex rates up to 1:8

NXP Semiconductors
PCF8537
Industrial LCD driver for multiplex rates up to 1:8
R/W = 0
subaddress
001
control byte
CR
OS
RAM/command byte
M
L
S
S
B
B
EXAMPLES
a) transmit two bytes of display RAM data
001
01
RAM DATA
RAM DATA
b) transmit two command bytes
001
10
COMMAND
00
c) transmit one command byte and two display RAM date bytes
001
10
COMMAND
01
Data transfers are terminated by de-asserting CE (set CE to logic 1)
Fig 49. SPI-bus write example
COMMAND
RAM DATA
RAM DATA
013aaa656
R/W SA
unused
command byte
multiplex drive mode = 1:8 M[2:0] = 111
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
001000000000000000000111
SCL
SDIO
CE
013aaa657
In this example, the multiplex mode is set to 1:8. The transfer is terminated by CE returning to logic 1. After the last bit is
transmitted, the state of the SDIO line is not important.
Fig 50. SPI-bus write example
9.3.2 Data read
The temperature readout data byte TD[7:0] can be read from the PCF8537BH.
A readout is initiated by sending the subaddress byte with the R/W bit set high. The
transmission is controlled by the active LOW chip enable signal CE.
After the last bit of the subaddress byte is transmitted, the PCF8537BH will immediately
start to drive the SDIO line. It is only necessary to read the values once, however since
the update of the register is asynchronous to the interface clock, it is recommended to
read the register twice and check for a stable value.
The readout is terminated by asserting CE. At this time, the SDIO bus is released. It is
important that the bus is not left floating and that the microcontroller then takes over
driving of the bus.
PCF8537
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
© NXP B.V. 2012. All rights reserved.
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