UM10204 Datasheet, PDF (57/64 Pages) NXP Semiconductors – I2C-bus specification and user manual

NXP Semiconductors
UM10204
I²C-bus specification and user manual
capacitance. Keep in mind that adding a buffer always adds delays — a buffer delay plus
an additional transition time to each edge, which reduces the maximum operating
frequency and may also introduce special V_IL and V_OL considerations.
Refer to application notes AN255, I²C / SMBus Repeaters, Hubs and Expanders and
AN262, PCA954x Family of I²C / SMBus Multiplexers and Switches for more details on
this subject and the devices available from NXP Semiconductors.
V_DD1
V_DD2
SDA
SCL
400 pF
BUFFER
400 pF
slaves and masters
slaves and masters
Remark: Some buffers allow V_DD1 and V_DD2 to be different levels.
Fig 43. Using a buffer to divide bus capacitance
002aac882
7.2.4 Switched pull-up circuit
The supply voltage (V_DD) and the maximum output LOW level determine the minimum
value of pull-up resistor R_p (see Section 7.1). For example, with a supply voltage of
V_DD = 5 V ± 10 % and V_OL(max) = 0.4 V at 3 mA, R_p(min) = (5.5 − 0.4) / 0.003 = 1.7 kΩ. As
shown in Figure 42, this value of R_p limits the maximum bus capacitance to about 200 pF
to meet the maximum t_r requirement of 300 ns. If the bus has a higher capacitance than
this, a switched pull-up circuit (as shown in Figure 44) can be used.
1/4 HCT4066
nE
P
nY
V_CC
N
V_DD
5V 10 %
nZ
GND
1.3 kΩ _Rp2
100 Ω _{R s} 100 Ω _{R s}
1.7 kΩ
R _p1
SDA or SCL
bus line
I/O
I/O
N
N
Cb
400 pF
max.
FAST - MODE I²C BUS DEVICES
V_SS
mbc620
Fig 44. Switched pull-up circuit
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 13 February 2012
© NXP B.V. 2012. All rights reserved.
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