LPC1315 Datasheet, PDF (56/77 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM

NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
10.6 SSP interface
Table 16. Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Conditions
SSP master
T_cy(clk)
clock cycle time
full-duplex mode
[1]
when only transmitting ^[1]
t_DS
data set-up time
t_DH
t_v(Q)
t_h(Q)
SSP slave
data hold time
data output valid time
data output hold time
in SPI mode;
[2]
2.4 V  V_DD  3.6 V
2.0 V  V_DD < 2.4 V ^[2]
in SPI mode
[2]
in SPI mode
[2]
in SPI mode
[2]
T_cy(PCLK)
PCLK cycle time
t_DS
data set-up time
in SPI mode
[3][4]
t_DH
data hold time
in SPI mode
[3][4]
t_v(Q)
data output valid time in SPI mode
[3][4]
t_h(Q)
data output hold time in SPI mode
[3][4]
Min
40
27.8
15
20
0
-
0
13.9
0
3  T_cy(PCLK) + 4
-
-
Max
Unit
-
ns
-
ns
-
ns
-
ns
-
ns
10
ns
-
ns
-
ns
-
ns
-
ns
3  T_cy(PCLK) + 11 ns
2  T_cy(PCLK) + 5
ns
[1] T_cy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f_main. The clock cycle time derived from the SPI bit rate T_cy(clk) is a function of the
main clock frequency f_main, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] T_amb = 40 C to 85 C.
[3] T_cy(clk) = 12  T_cy(PCLK).
[4] T_amb = 25 C; V_DD = 3.3 V.
LPC1315_16_17_45_46_47
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 September 2012
© NXP B.V. 2012. All rights reserved.
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