ISP1506A Datasheet, PDF (50/79 Pages) NXP Semiconductors – ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
Table 34.
Bit
Symbol
Reset
Access
USB Interrupt Status register (address R = 13h) bit allocation
7
6
5
4
3
reserved
ID_GND
SESS_
END
X
X
X
0
0
R
R
R
R
R
2
SESS_
VALID
0
R
1
VBUS_
VALID
0
R
0
HOST_
DISCON
0
R
Table 35. USB Interrupt Status register (address R = 13h) bit description
Bit
Symbol
Description
7 to 5 -
reserved
4
ID_GND
ID Ground: Reflects the current value of the ID detector circuit.
3
SESS_END
Session End: Reflects the current value of the session end voltage comparator.
2
SESS_VALID Session Valid: Reflects the current value of the session valid voltage comparator.
1
VBUS_VALID V_BUS Valid: Reflects the current value of the V_BUS valid voltage comparator.
0
HOST_DISCON Host Disconnect: Reflects the current value of the host disconnect detector.
10.1.8 USB Interrupt Latch register
The bits of the USB Interrupt Latch register are automatically set by the ISP1506 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1506 will
automatically clear all bits when the link reads this register, or when the PHY enters
low-power mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in Table 36.
Table 36.
Bit
Symbol
Reset
Access
USB Interrupt Latch register (address R = 14h) bit allocation
7
6
5
4
3
reserved
ID_GND_L
SESS_
END_L
0
0
0
0
0
R
R
R
R
R
2
SESS_
VALID_L
0
R
1
VBUS_
VALID_L
0
R
0
HOST_
DISCON_L
0
R
Table 37. USB Interrupt Latch register (address R = 14h) bit description
Bit Symbol
Description
7 to 5 reserved
-
4
ID_GND_L
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
3
SESS_END_L
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
2
SESS_VALID_L Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
1
VBUS_VALID_L V_BUS Valid Latch: Automatically set when an unmasked event occurs on VBUS_VLD.
Cleared when this register is read.
0
HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
ISP1506A_ISP1506B_1
Product data sheet
Rev. 01 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
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