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| PCAL6416A Datasheet, PDF (5/54 Pages) NXP Semiconductors – Low-voltage translating 16-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers | |||
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NXP Semiconductors
5. Pinning information
5.1 Pinning
PCAL6416A
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
INT 1
VDD(I2C-bus) 2
RESET 3
P0_0 4
P0_1 5
P0_2 6
P0_3 7
P0_4 8
P0_5 9
P0_6 10
P0_7 11
VSS 12
PCAL6416APW
24 VDD(P)
23 SDA
22 SCL
21 ADDR
20 P1_7
19 P1_6
18 P1_5
17 P1_4
16 P1_3
15 P1_2
14 P1_1
13 P1_0
002aaf963
Fig 2. Pin configuration for TSSOP24
terminal 1
index area
P0_0 1
P0_1 2
P0_2 3
P0_3 4
P0_4 5
P0_5 6
PCAL6416AHF
18 ADDR
17 P1_7
16 P1_6
15 P1_5
14 P1_4
13 P1_3
Transparent top view
002aaf964
Fig 3.
The exposed center pad, if used, must be
connected only as a secondary ground or
must be left electrically open.
Pin configuration for HWQFN24
ball A1
index area
PCAL6416AEV
1
2
3
4
5
A
B
C
D
E
Transparent top view
002aaf966
Fig 4. Pin configuration for VFBGA24
(3 mm ï´ 3 mm)
1
2
3
A P0_0 RESET
INT
4
5
SDA SCL
B P0_2
VDD(I2C-bus) VDD(P) ADDR
C P0_3 P0_4
P0_1
P1_7 P1_6
D P0_5 P0_7
P1_2
P1_4 P1_5
E P0_6 VSS
P1_0
P1_1 P1_3
002aag244
Fig 5.
An empty cell indicates no ball
is populated at that grid point.
Ball mapping for 3 mm ï´ 3 mm
VFBGA24 (transparent top view)
PCAL6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 â 24 December 2012
© NXP B.V. 2012. All rights reserved.
5 of 54
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