PCA9543A_09 Datasheet, PDF (5/23 Pages) NXP Semiconductors – 2-channel I2C-bus switch with interrupt logic and reset

NXP Semiconductors
PCA9543A/43B/43C
2-channel I²C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9543A/43B/43C”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9543A is shown in Figure 4. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1 1 1 0 0 A1 A0 R/W
fixed
hardware
selectable
002aab169
Fig 4. Slave address PCA9543A
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
The PCA9543B and PCA9543C are alternate address versions if needed for larger
systems or to resolve address conflicts. The data sheet will reference the PCA9543A, but
the PCA9543B and PCA9543C function identically except for the slave address.
1 1 1 1 0 A1 A0 R/W
fixed
hardware
selectable
002aab799
Fig 5. Slave address PCA9543B
0 1 1 0 0 A1 A0 R/W
fixed
hardware
selectable
002aab800
Fig 6. Slave address PCA9543C
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9543A, which will be stored in the control register. If multiple bytes are
received by the PCA9543A, it will save the last byte received. This register can be written
and read via the I²C-bus.
PCA9543A_43B_43C_6
Product data sheet
interrupt bits
(read only)
channel selection bits
(read/write)
76543210
X
X
INT INT
10
X
X B1 B0
channel 0
channel 1
INT0
INT1
002aab181
Fig 7. Control register
Rev. 06 — 15 June 2009
© NXP B.V. 2009. All rights reserved.
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