PCA9516A Datasheet, PDF (5/19 Pages) NXP Semiconductors – 5-channel I2C hub

NXP Semiconductors
PCA9516A
5-channel I²C-bus hub
6. Functional description
The PCA9516A is a five-way hub repeater, which enables I²C-bus and similar bus
systems to be expanded with only one repeater delay and no functional degradation of
system performance.
The PCA9516A contains five bidirectional, open-drain buffers specifically designed to
support the standard low-level-contention arbitration of the I²C-bus. Except during
arbitration or clock stretching, the PCA9516A acts like five pairs of non-inverting,
open-drain buffers, one for SDA and one for SCL. Refer to Figure 1 “Block diagram”.
6.1 Enable
The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.
Each enable pin ENn controls its associated SDAn and SCLn ports. When LOW, the ENn
pin blocks the inputs from SDAn and SCLn as well as disabling the output drivers on the
SDAn and SCLn pins. The enable pins should only change state when both the global bus
and the local port are in an idle state to prevent system failures.
The active HIGH enable pins allow the use of open-drain drivers which can be wire-ORed
to create a distributed enable where either centralized control signal (master) or spoke
signal (submaster) can enable the channel when it is idle.
6.2 I²C-bus systems
As with the standard I²C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector configuration of the I²C-bus.)
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part is designed to work with Standard-mode and
Fast-mode I²C-bus devices in addition to SMBus devices. Standard-mode I²C-bus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic
I²C-bus system where Standard-mode devices and multiple masters are possible. Please
see application note AN255, “I²C/SMBus Repeaters, Hubs and Expanders” for additional
information on sizing resistors and precautions when using more than one
PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction
with the P82B96.
7. Application design-in information
A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I²C-bus while the slave is connected to a 5 V bus. All buses run at 100 kHz
unless slave 3 is isolated, and then the master bus and slave 1 and slave 2 can run at
400 kHz.
Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves
can be located on all five segments with 400 pF load allowed on each segment.
Unused ports should be isolated by holding the enable pin (ENn) to GND and/or pulling
SDAn/SCLn pins to V_CC through appropriately sized resistors. The primary bus master is
normally connected to SDA0/SCL0. If the SDA0/SCL0 port is not used, the pins need to
be pulled to V_CC through appropriately sized resistors.
PCA9516A_3
Product data sheet
Rev. 03 — 23 April 2009
© NXP B.V. 2009. All rights reserved.
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